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INTEGRATED CIRCUITS
SA56615-XX; SA56616-XX CMOS system reset with adjustable delay time
Product data 2002 Mar 25
Philips Semiconductors
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
GENERAL DESCRIPTION
The SA56616-XX and SA56615-XX CMOS system resets have low consumption current of typically 1.0 A and high precision detection voltage within 2%. The delay time is adjusted by an external capacitor working in conjunction with the on-chip delay network. The SA56615-XX and SA56616-XX have different output configurations to accommodate a wide variety of microprocessors and logic devices. The SA56615-XX incorporates a low side open-drain output topology which requires a pull-up resistor to VDD, while the SA56616-XX incorporates an active push-pull totem pole output topology comprised of complimentary P-channel and N-channel FETs. The resets operate over a wide operating supply voltage range from 0.7 V to 10 V. Reset detection voltages are available at 0.9 V, 1.8 V, 1.9 V, 2.0 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.2 V, 4.3 V, 4.4 V, 4.5 V, 4.6 V and 4.7 V. Other thresholds are offered upon request at 100 mV increments from 0.9 V to 6.0 V. The device comes in the small SOT23-5 package.
FEATURES
* Super low supply current: typically 1.0 A (VDD = VS + 1 V) * Operating supply voltage range: 0.7 V to 10 V * High precision detection voltage: 2% * Detection voltage: 0.9 V, 1.8 V, 1.9 V, 2.0 V, 2.7 V, 2.8 V, 2.9 V,
3.0 V, 3.1 V, 4.2 V, 4.3 V, 4.4 V, 4.5 V, 4.6 V, and 4.7 V
APPLICATIONS
* Microprocessor and logic circuit reset * Battery voltage level detection * Battery backup and switching circuits * Adjustable time delay circuits
* Other detection threshold voltages available at 100 mV steps from
0.9 V to 6.0 V
* User adjustable reset delay time * Versatile output configurations:
- SA56615-XX: open-drain - SA56616-XX: N-channel/P-channel push-pull
SIMPLIFIED SYSTEM DIAGRAMS
VDD VDD 2 VIN CD OUT RPU RESET LOGIC SYSTEM VIN CD VDD 2 OUT RESET LOGIC SYSTEM VDD
5
SA56615-XX
1
5
SA56616-XX
1
3 GND GND
3
SL01596
SL01597
Figure 1. SA56615-XX simplified system diagram.
Figure 2. SA56616-XX simplified system diagram.
2002 Mar 25
2
853-2332 27919
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
ORDERING INFORMATION
TYPE NUMBER SA56615-XXD SA56616-XXD PACKAGE NAME SOT23-5, SOT25, SO5 SOT23-5, SOT25, SO5 DESCRIPTION plastic small outline package; 5 leads (see dimensional drawing) plastic small outline package; 5 leads (see dimensional drawing) TEMPERATURE RANGE -40 to +85 C -40 to +85 C
NOTE: The device has 15 voltage output options, indicated by the XX on the `Type number'. XX 09 18 19 20 27 28 29 30 31 42 43 44 45 46 47 VOLTAGE (Typical) 0.9 V 1.8 V 1.9 V 2.0 V 2.7 V 2.8 V 2.9 V 3.0 V 3.1 V 4.2 V 4.3 V 4.4 V 4.5 V 4.6 V 4.7 V
PIN CONFIGURATION
PIN DESCRIPTION
PIN SYMBOL OUT VDD GND N/C CD DESCRIPTION Output. RESET Active-LOW. Power supply voltage. Ground. Negative supply. No connection. Time delay pin. Delay adjusted by capacitor to ground. 1 2
OUT
1
5
CD
VDD
2
SA56615-XX SA56616-XX
4 N/C
3 4
GND
3
5
SL01595
Figure 3. Pin configuration.
2002 Mar 25
3
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
MAXIMUM RATINGS
SYMBOL VDD(max) VOUT Power supply voltage Output voltage SA56615-XX SA56616-XX IOUT Vi(CD) Tamb Tstg P Output current CD pin input voltage Ambient operating temperature Storage temperature Power dissipation PARAMETER MIN. - VSS + 0.3 VSS - 0.3 - VSS - 0.3 -40 -40 - MAX. +12 12 12 70 VDD + 0.3 85 125 150 UNIT V V V mA V C C mW
ELECTRICAL CHARACTERISTICS
Tamb = 25 C, unless otherwise specified. SYMBOL Vhys VS/T ISS1 ISS2 IOUT1 IOUT2 IOUT3 VTCD ICD1 ICD2 VDDL1 VDDL2 RD ILEAK PARAMETER Hysteresis voltage Detection voltage temperature coefficient Supply current 1 Supply current 2 Output current 1 Output current 2 Output current 3 Delay threshold voltage Delay output current 1 Delay output current 2 Minimum supply voltage 1 Minimum supply voltage 2 Delay CD Pin Resistance Output leakage current VDD = 10 V; VCD = 10 V; VDS = 10 V -40 C Tamb 85 C VDD = (VSL) - 0.13 V VDD = (VSL) + 2.0 V Nch: VDS = 0.05 V; VDD = 0.7 V VDD = 1.5 V; Nch: VDS = 0.05 V; VDD = 1.5 V VDD = 4.5 V; Pch: VDS = -2.1 V (Note 1) VDD = (VSL) x 1.1 V VDS = 0.1 V; VDD = 0.7 V VDS = 0.5 V; VDD = 0.7 V VOUT 0.1 V; Tamb = 25 C VOUT 0.1 V; -40 C Tamb 85 C CONDITIONS MIN. VS x 0.03 - - - 0.01 1.0 1.0 VDD x 0.4 2 200 - - 0.5 - TYP. VS x 0.05 0.01 4 1.2 0.05 2.0 2.0 VDD x 0.5 30 800 0.55 0.65 1.0 - MAX. VS x 0.07 - 8 3.6 - - - VDD x 0.6 - - 0.70 0.80 2.0 0.1 UNIT V %/C A A mA mA mA V A A V V M A
NOTE: 1. Output current 3 is SA56616-XX CMOS push-pull configuration only.
2002 Mar 25
4
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TYPICAL PERFORMANCE CURVES
NOTE: Typical characteristics for SA56616-09
1.0 0.9 0.8 OUTPUT VOLTAGE (V) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.70 0 0.75 0.80 0.85 0.90 0.95 1.00 0 2 4 6 8 10 CONSUMPTION CURRENT ( A) INPUT VOLTAGE (V) 2.0
1.5
1.0
0.5
TEMPERATURE (C)
SL01743
SL01744
Figure 4. Output voltage versus input voltage.
Figure 5. Consumption current versus input voltage.
0.40 VDS = 0.5 V CD PIN OUTPUT CURRENT (mA) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 DELAY TIME (ms)
1000
100
10
1
0
0.2
0.4
0.6
0.8
1.0
0.1 0.0001
0.001
0.01 CD (F)
0.1
1
INPUT VOLTAGE (V)
SL01745
SL01746
Figure 6. CD pin output current versus input voltage.
Figure 7. Delay time versus CD.
1.00
80 70 HYSTERESIS VOLTAGE (mV)
DETECTING VOLTAGE (V)
0.95
60 50 40 30 20 10
0.90
0.85
0.80 -40
-20
0
20
40
60
80
100
0 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01747
SL01748
Figure 8. Detection voltage versus temperature.
Figure 9. Hysteresis voltage versus temperature.
2002 Mar 25
5
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TYPICAL PERFORMANCE CURVES (continued)
NOTE: Typical characteristics for SA56616-09
0.20 1.0
OUTPUT CURRENT 1 (mA)
0.15
OUTPUT CURRENT 2 (mA) -20 0 20 40 60 80 100
0.8
0.6
0.10
0.4
0.05
0.2
0.00 -40
0.0 -40 -20 0 20 40 60 80 100
TEMPERATURE (C)
TEMPERATURE (C)
SL01749
SL01750
Figure 10. Output current 1 versus temperature.
Figure 11. Output current 2 versus temperature.
5.0 CD PIN THRESHOLD VOLTAGE (V) -20 0 20 40 60 80 100 4.5 OUTPUT CURRENT 3 (mA) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -40
0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01751
SL01752
Figure 12. Output current 3 versus temperature.
Figure 13. CD pin threshold voltage versus temperature.
0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -40
100 90 80 70 60 50 40 30 20 10 0 -40 -20 0 20 40 60 80 100 CD PIN OUTPUT CURRENT 2 (mA) CD PIN OUTPUT CURRENT 1 ( A)
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01753
SL01754
Figure 14. CD pin output current 1 versus temperature.
Figure 15. CD pin output current 2 versus temperature.
2002 Mar 25
6
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TYPICAL PERFORMANCE CURVES (continued)
NOTE: Typical characteristics for SA56616-28
3.0 3.0
CONSUMPTION CURRENT ( A)
2.5 OUTPUT VOLTAGE (V)
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0 1.0 1.5 2.0 INPUT VOLTAGE (V) 2.5 3.0
0 0 2 4 6 8 10 INPUT VOLTAGE (V)
SL01755
SL01756
Figure 16. Output voltage versus input voltage.
Figure 17. Consumption current versus input voltage.
4.0 VDS = 0.5 V CD PIN OUTPUT CURRENT (mA)
1000
3.0 DELAY TIME (ms)
100
2.0
10
1.0
1
0.0 0 0.5 1.0 1.5 2.0 2.5 3.0
0.1 0.0001
0.001
0.01 CD (F)
0.1
1
INPUT VOLTAGE (V)
SL01757
SL01758
Figure 18. CD pin output current versus input voltage.
Figure 19. Delay time versus CD.
3.00
200
2.90
HYSTERESIS VOLTAGE (mV) -20 0 20 40 60 80 100
180
DETECTING VOLTAGE (V)
160
2.80
140
120 100
2.70
2.60 -40
80 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01759
SL01760
Figure 20. Detection voltage versus temperature.
Figure 21. Hysteresis voltage versus temperature.
2002 Mar 25
7
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TYPICAL PERFORMANCE CURVES (continued)
NOTE: Typical characteristics for SA56616-28
0.20 8.0 7.0 OUTPUT CURRENT 1 (mA) OUTPUT CURRENT 2 (mA) -20 0 20 40 60 80 100 0.15 6.0 5.0 4.0 3.0 2.0 1.0 0.00 -40 0.0 -40
0.10
0.05
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01761
SL01762
Figure 22. Output current 1 versus temperature.
Figure 23. Output current 2 versus temperature.
5.0 CD PIN THRESHOLD VOLTAGE (V) -20 0 20 40 60 80 100
1.80
OUTPUT CURRENT 3 (mA)
4.0
1.70
1.60
3.0
1.50
2.0
1.40 1.30
1.0
0.0 -40
1.20 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01763
SL01764
Figure 24. Output current 3 versus temperature.
Figure 25. CD pin threshold voltage versus temperature.
100
3.0 CD PIN OUTPUT CURRENT 2 (mA)
CD PIN OUTPUT CURRENT 1 ( A)
2.5
80
2.0
60
1.5
1.0
40
0.5
20 -40
-20
0
20
40
60
80
100
0.0 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01765
SL01766
Figure 26. CD pin output current 1 versus temperature.
Figure 27. CD pin output current 2 versus temperature.
2002 Mar 25
8
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TYPICAL PERFORMANCE CURVES (continued)
NOTE: Typical characteristics for SA56616-46
5.0 4.5 4.0 OUTPUT VOLTAGE (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 2 3 INPUT VOLTAGE (V) 4 5 CONSUMPTION CURRENT ( A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 2 4 6 8 10
INPUT VOLTAGE (V)
SL01767
SL01768
Figure 28. Output voltage versus input voltage.
Figure 29. Consumption current versus input voltage.
6.0 CD PIN OUTPUT CURRENT (mA)
VDS = 0.5 V
1000
5.0 100 4.0 DELAY TIME (s)
3.0
10
2.0
1 1.0
0.0 0 1 2 3 4 5
0.1 0.0001
0.001
0.01 CD (F)
0.1
1
INPUT VOLTAGE (V)
SL01769
SL01770
Figure 30. CD pin output current versus input voltage.
Figure 31. Delay time versus CD.
5.0
300 280
4.8
HYSTERESIS VOLTAGE (mV) -20 0 20 40 60 80 100
DETECTING VOLTAGE (V)
260 240 220 200 180
4.6
4.4
4.2 -40
160 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01771
SL01772
Figure 32. Detection voltage versus temperature.
Figure 33. Hysteresis voltage versus temperature.
2002 Mar 25
9
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TYPICAL PERFORMANCE CURVES (continued)
NOTE: Typical characteristics for SA56616-46
0.20 8.0 7.0 OUTPUT CURRENT 1 (mA) OUTPUT CURRENT 2 (mA) -20 0 20 40 60 80 100 0.15 6.0 5.0 4.0 3.0 2.0 1.0 0.00 -40 0.0 -40
0.10
0.05
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01773
SL01774
Figure 34. Output current 1 versus temperature.
Figure 35. Output current 2 versus temperature.
8.0 CD PIN THRESHOLD VOLTAGE (V) 7.0 OUTPUT CURRENT 3 (mA) 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -40
2.80
2.75
2.70
2.65
-20
0
20
40
60
80
100
2.60 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01775
SL01776
Figure 36. Output current 3 versus temperature.
Figure 37. CD pin threshold voltage versus temperature.
100 CD PIN OUTPUT CURRENT 2 (mA) -20 0 20 40 60 80 100 CD PIN OUTPUT CURRENT 1 ( A)
2.5
2.0
80
1.5
60
1.0
40
0.5
20 -40
0.0 -40 -20 0 20 40 60 80 100
TEMPERATURE (C)
TEMPERATURE (C)
SL01777
SL01778
Figure 38. CD pin output current 1 versus temperature.
Figure 39. CD pin output current 2 versus temperature.
2002 Mar 25
10
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TYPICAL PERFORMANCE CURVES (continued)
NOTE: Typical characteristics for SA56615-09
1.0 0.9 0.8 OUTPUT VOLTAGE (V) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 0.6 0.8 1.0 0 0 2 4 6 8 10 CONSUMPTION CURRENT ( A) INPUT VOLTAGE (V) 2.0
1.5
1.0
0.5
TEMPERATURE (C)
SL01779
SL01780
Figure 40. Output voltage versus input voltage.
Figure 41. Consumption current versus input voltage.
0.40 VDS = 0.5 V CD PIN OUTPUT CURRENT (mA) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 DELAY TIME (ms)
1000
100
10
1
0
0.2
0.4
0.6
0.8
1.0
0.1 0.0001
0.001
0.01 CD (F)
0.1
1
INPUT VOLTAGE (V)
SL01781
SL01782
Figure 42. CD pin output current versus input voltage.
Figure 43. Delay time versus CD.
1.00
80 70 HYSTERESIS VOLTAGE (mV)
DETECTING VOLTAGE (V)
0.95
60 50 40 30 20 10
0.90
0.85
0.80 -40
-20
0
20
40
60
80
100
0 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01783
SL01784
Figure 44. Detection voltage versus temperature.
Figure 45. Hysteresis voltage versus temperature.
2002 Mar 25
11
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TYPICAL PERFORMANCE CURVES (continued)
NOTE: Typical characteristics for SA56615-09
0.20 1.0
OUTPUT CURRENT 1 (mA)
0.15
OUTPUT CURRENT 2 (mA) -20 0 20 40 60 80 100
0.8
0.6
0.10
0.4
0.05
0.2
0.00 -40
0.0 -40 -20 0 20 40 60 80 100
TEMPERATURE (C)
TEMPERATURE (C)
SL01785
SL01786
Figure 46. Output current 1 versus temperature.
Figure 47. Output current 2 versus temperature.
0.60 CD PIN THRESHOLD VOLTAGE (V) 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 -40
100 90 CD PIN OUTPUT CURRENT 1 ( A) 80 70 60 50 40 30 20 10 -20 0 20 40 60 80 100 0 -40 -20 0 20 40 60 80 100
TEMPERATURE (C)
TEMPERATURE (C)
SL01787
SL01788
Figure 48. CD pin threshold voltage versus temperature.
0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -40
Figure 49. CD pin output current 1 versus temperature.
CD PIN OUTPUT CURRENT 2 (mA)
-20
0
20
40
60
80
100
TEMPERATURE (C)
SL01789
Figure 50. CD pin output current 2 versus temperature.
2002 Mar 25
12
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TYPICAL PERFORMANCE CURVES (continued)
NOTE: Typical characteristics for SA56615-28
3.0 3.0
2.5 OUTPUT VOLTAGE (V)
CONSUMPTION CURRENT ( A)
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0 0.0
0 0.5 1.0 1.5 2.0 2.5 3.0 0 2 4 6 8 10 INPUT VOLTAGE (V) INPUT VOLTAGE (V)
SL01790
SL01791
Figure 51. Output voltage versus input voltage.
Figure 52. Consumption current versus input voltage.
4.0 VDS = 0.5 V CD PIN OUTPUT CURRENT (mA)
1000
3.0 DELAY TIME (ms)
100
2.0
10
1.0
1
0.0 0 0.5 1.0 1.5 2.0 2.5 3.0
0.1 0.0001
0.001
0.01 CD (F)
0.1
1
INPUT VOLTAGE (V)
SL01792
SL01793
Figure 53. CD pin output current versus input voltage.
Figure 54. Delay time versus CD.
3.00
200
2.90
HYSTERESIS VOLTAGE (mV) -20 0 20 40 60 80 100
180
DETECTING VOLTAGE (V)
160
2.80
140
120 100
2.70
2.60 -40
80 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01794
SL01795
Figure 55. Detection voltage versus temperature.
Figure 56. Hysteresis voltage versus temperature.
2002 Mar 25
13
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TYPICAL PERFORMANCE CURVES (continued)
NOTE: Typical characteristics for SA56615-28
0.20 8.0 7.0 OUTPUT CURRENT 1 (mA) OUTPUT CURRENT 2 (mA) -20 0 20 40 60 80 100 0.15 6.0 5.0 4.0 3.0 2.0 1.0 0.00 -40 0.0 -40
0.10
0.05
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01796
SL01797
Figure 57. Output current 1 versus temperature.
Figure 58. Output current 2 versus temperature.
1.80 CD PIN THRESHOLD VOLTAGE (V)
100 CD PIN OUTPUT CURRENT 1 ( A) -20 0 20 40 60 80 100
1.70
80
1.60
1.50
60
1.40 1.30
40
1.20 -40
20 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01798
SL01799
Figure 59. CD pin threshold voltage versus temperature.
Figure 60. CD pin output current 1 versus temperature.
3.0 CD PIN OUTPUT CURRENT 2 (mA)
2.5
2.0
1.5
1.0
0.5
0.0 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
SL01800
Figure 61. CD pin output current 2 versus temperature.
2002 Mar 25
14
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TYPICAL PERFORMANCE CURVES (continued)
NOTE: Typical characteristics for SA56615-46
5.0 4.5 4.0 OUTPUT VOLTAGE (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 INPUT VOLTAGE (V) CONSUMPTION CURRENT ( A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 2 4 6 8 10
INPUT VOLTAGE (V)
SL01801
SL01802
Figure 62. Output voltage versus input voltage.
Figure 63. Consumption current versus input voltage.
6.0 CD PIN OUTPUT CURRENT (mA)
VDS = 0.5 V
1000
5.0 100 4.0 DELAY TIME (ms)
3.0
10
2.0
1 1.0
0.0 0 1 2 3 4 5
0.1 0.0001
0.001
0.01 CD (F)
0.1
1
INPUT VOLTAGE (V)
SL01803
SL01804
Figure 64. CD pin output current versus input voltage.
Figure 65. Delay time versus CD.
5.0
300 280
4.8
HYSTERESIS VOLTAGE (mV) -20 0 20 40 60 80 100
DETECTING VOLTAGE (V)
260 240 220 200 180
4.6
4.4
4.2 -40
160 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01805
SL01806
Figure 66. Detection voltage versus temperature.
Figure 67. Hysteresis voltage versus temperature.
2002 Mar 25
15
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TYPICAL PERFORMANCE CURVES (continued)
NOTE: Typical characteristics for SA56615-46
0.20 8.0 7.0 OUTPUT CURRENT 1 (mA) OUTPUT CURRENT 2 (mA) -20 0 20 40 60 80 100 0.15 6.0 5.0 4.0 3.0 2.0 1.0 0.00 -40 0.0 -40
0.10
0.05
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01807
SL01808
Figure 68. Output current 1 versus temperature.
Figure 69. Output current 2 versus temperature.
2.80 CD PIN THRESHOLD VOLTAGE (V)
100 CD PIN OUTPUT CURRENT 1 ( A) -20 0 20 40 60 80 100
2.75
80
2.70
60
2.65
40
2.60 -40
20 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
SL01809
SL01810
Figure 70. CD pin threshold voltage versus temperature.
Figure 71. CD pin output current 1 versus temperature.
2.5 CD PIN OUTPUT CURRENT 2 (mA)
2.0
1.5
1.0
0.5
0.0 -40 -20 0 20 40 60 80 100
TEMPERATURE (C)
SL01811
Figure 72. CD pin output current 2 versus temperature.
2002 Mar 25
16
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TECHNICAL DISCUSSION
The SA56616-XX and SA56615-XX are CMOS devices designed to monitor the system's power source and provide a system reset function in the event the supply voltage sags below an acceptable level for the system to reliably operate. The SA56616-XX and SA56615-XX generate a compatible reset signal for a wide variety of microprocessors and logic systems. They can operate up to 10 volts. The series includes several versions providing high precision reset threshold levels of 0.9, 1.8, 1.9, 2.0, 2.7, 2.8, 2.9, 3.0, 3.1, 4.2, 4.3, 4.4, 4.5, 4.6, and 4.7 V. The reset threshold incorporates a typical hysteresis of (VS x 0.05) volts to prevent erratic resets from being generated. The SA56616-XX and SA56615-XX operate at very low supply currents, typically 1.2 A, while offering high precision of threshold detection, typically 2%. They have an on-chip reset time delay which is adjusted by an external capacitor. The SA56616-XX and SA56615-XX offer different output options; one or the other may be preferred depending on the system criteria. The SA56616-XX (Figure 2) incorporates an active push-pull, Totem-pole output topology comprised of complimentary P-channel and N-channel FETs. A P-channel is on the high supply side and when ON pulls the output to or near the VDD supply voltage from which output source current can be obtained. A complimentary N-channel FET is on the low supply side or ground side, and actively pulls the output LOW or to ground with the capability of sinking current into the output. When connecting the SA56616-XX to a system, the user should be aware of the effect of supplying source current from the output of the SA56616-XX on the system. The SA56615-XX (Figure 1) incorporates a low side N-channel open-drain topology, which requires an external pull-up to VDD. Though this may be regarded as a disadvantage, it is an advantage in many sensitive applications because the open-drain output can not source reset current to a microprocessor when both are operated from a common supply. For this reason, the SA56615-XX offers a safe interconnect to a wide variety of microprocessors. Figure 73 and Figure 74 are the functional block diagrams of the SA56615-XX and SA56616-XX, respectively. The only difference between them is the output configuration. The internal reference is typically 0.8 V over the operating temperature range. The reference voltage is connected to the non-inverting input of the threshold comparator while the inverting input monitors the supply voltage through a resistor divider network made up of R1, R2, and R3. The output threshold comparator drives the time delay/inverting amplifier network and, in turn, the totem-pole output stage. When the supply voltage sags to the threshold detection voltage, the resistor divider network supplies a voltage to the inverting input of the threshold comparator which is less than VREF, causing the
output of the comparator to go HIGH. This switches the N-channel FET (M3) to an active ON state, pulling its output (drain) to a low voltage state. The output of M3 is connected to the internal resistor, RD, the time delay pin CD, and the input of the inverting amplifier. The output level of the CD pin will rise to the level of VTCD by the time constant formed by internal RD to VDD and external CD to ground. The output of the inverting amplifier will then be pulled to a LOW state. This causes the high side FET M1 of the totem-pole output stage to turn off while simultaneously turning the low side N-channel FET M2 to an active ON state, pulling the output to a low voltage state. The device adheres to true input/output logic protocol. The output goes to a low voltage state when the input is LOW (below VSL) and the output goes HIGH when the input is HIGH (above VSH). The low side N-channel FET (M4) establishes threshold hysteresis by turning ON whenever the threshold comparator output goes to a HIGH state (when VDD sags to or below the VSL level). With M4 in the ON state, additional current flows through resistors R1 and R2 which causes the inverting input of the threshold comparator to be pulled even lower. For the comparator to reverse its output polarity and turn OFF M4, the VDD source voltage must overcome this additional pull-down voltage on the comparator's inverting input. The differential voltage required to do this establishes the hysteresis voltage of the sensed threshold voltage. Typically, this is (VS x 0.5) volts. When the VDD voltage sags and is at or below the Detection Threshold (VSL), the device will assert a Reset Low output at or very near ground potential. As the VDD voltage rises from (VDD < VSL) to VSH or higher, the reset is released and the output follows VDD. Conversely, decreases in VDD from (VDD > VSL) to VSL or lower cause the output to be pulled to ground. Hysteresis Voltage = Release Voltage - Detection Threshold Voltage Vhys = VSH - VSL where: VSH = VSL + Vhys = VREF(R1 + R2)/R2 VSL = VREF(R1 + R2 + R3)/(R2 +R3) When VDD drops below the minimum operating voltage, typically less than 0.95 volts, the output is undefined and output reset low assertion is not guaranteed. At this level of VDD the output will try to rise to VDD. The VREF voltage is typically 0.8 V. The devices are fabricated using a high resistance CMOS process and utilize high resistance R1, R2, and R3 values requiring very small amounts of current. This combination achieves very efficient low power performance over the full temperature.
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Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
Equivalent circuit diagrams
VDD
2 R1 RD 1 OUT
VDD
2 R1 M1 RD 1 OUT
R2 VREF M4 R3 GND 3 5 CD M3
M2 VREF
R2 M4 R3 GND 3 5
M2 M3
SL01598
CD
SL01599
Figure 73. SA56615-XX equivalent circuit.
Figure 74. SA56616-XX equivalent circuit.
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18
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
TIMING DIAGRAM
The Timing Diagram shown in Figure 75 depicts the operation of the device. Letters A - K on the TIME axis indicate specific events. A: At "A", VDD begins to increase. Initially, the VOUT voltage increases but abruptly decreases when VDD reaches the level (approximately 0.8 V) that activates the internal bias circuitry and RESET is asserted. B: At "B", VDD reaches the high side threshold level, VSH. At this point the reset delay timer is initiated and VTCD, delay pin threshold voltage begins to rise. VDD increases to its nominal operating level without releasing the reset. C: At "C", the delay pin threshold voltage is reached, and the IC releases the hold on the VOUT reset. The reset output voltage goes to VDD. D-E: At "D", VDD begins to fall, causing the reset output to follow. VDD continues to fall until the VSL, low side detection threshold level is reached at "E". This causes the a reset signal to be generated (VOUT reset goes LOW). E-F: Between "E" and "F", VDD starts rising. F-G: At "F", VDD rises to VSH. Once again, the IC initiates the reset delay timer and VTCD starts to rise until the delay pin threshold level is reached and the IC releases the hold on the VOUT reset. At "G", the reset output VOUT goes to VDD. G-H: Between "G" and "H", VOUT follow VDD. As long VDD remains above VSH, no reset signal will be triggered. Before VDD falls to the VSH threshold, it begins to rise, causing VOUT to follow it. At "H" VDD returns to its nominal operating level. J: At "J" VDD falls until the VSL threshold point is reached. At this level, a RESET signal is generated and VOUT goes LOW. K: At "K", the VDD voltage has decreased until normal internal circuit bias is unable to maintain a VOUT reset. As a result, VOUT may rise to less than 0.8 V. As VDD decreases further, VOUT reset also decreases to zero.
VSH VSL VDD Vhys
V
CD PIN THRESHOLD VOLTAGE (VTHCD)
VTCD
VTCD
OUT
tD V
tD
A t
B
C
D
E
F
G
H
J
K
SL01600
Figure 75. Timing diagram.
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19
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
APPLICATION INFORMATION
The SA56615-XX differs from the SA56616-XX in that it requires a VOUT (RESET) pull-up resistor from pin 1 to VDD. Typical value for RPU, the pull-up resistor, is 470 k. The reset delay time is the duration measured from the time VDD exceeds the upper detection threshold (VSH) and when reset release occurs (VOUT or RESET goes HIGH). Figures 76 and 77 show typical application circuits for the SA56615-XX and SA56616-XX in which the delay time is externally adjusted by a capacitor connected from CD (pin 5) to ground. The delay time may be varied from 150 ns to 1 second with the appropriate external capacitor. Typical capacitor value is from 100 pF to 1 F. Refer to "Delay time versus CD" in Typical Performance Curves for the various detection threshold voltages. The delay time is approximated by tD 1.2 x RD x CD where: RD is CD pin resistance (typically 1 M) CD is the external delay time capacitor The CD (delay pin) threshold voltage, VTCD is typically 0.5 x VDD. Figures 78 and 79 show the test circuits that are used to measure the reset delay time of the SA56615-XX and SA56616-XX respectively. The delay diagrams indicate how the measurement is to be made. The input voltage, VIN is switched from VSH + 2.0 V to 0.7 V. The delay time is measured from the falling edge of VIN to where the CD (delay pin) threshold voltage is 0.5 x VDD.
OUTPUT VOLTAGE VIN CD 5 VDD 2 OUT +5 V 470 k
SA56615-XX
1
CD GND
3
VSH +2.0 V INPUT VOLTAGE 0.7 V GND 100% 50% GND
SL01601
Figure 78. SA56615-XX delay time, tD test circuit and diagram.
VDD 2 VIN CD OUT
5
SA56616-XX
1
CD GND VDD VDD 2 VIN CD OUT RPU RESET LOGIC SYSTEM INPUT VOLTAGE
3
VSH +2.0 V
5
SA56615-XX
1
0.7 V GND 100% OUTPUT VOLTAGE 50% GND
3 GND
SL01602
Figure 79. SA56616-XX delay time, tD test circuit and diagram.
SL01596
Figure 76. SA56615-XX application circuit.
VDD VDD 2 VIN CD OUT RESET LOGIC SYSTEM
5
SA56616-XX
1
3 GND
SL01597
Figure 77. SA56616-XX application circuit.
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Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
PACKING METHOD
The SA56615-XX and SA56616-XX are packed in reels, as shown in Figure 80.
GUARD BAND
TAPE REEL ASSEMBLY
TAPE DETAIL
COVER TAPE
CARRIER TAPE
BARCODE LABEL
BOX
SL01305
Figure 80. Tape and reel packing method.
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21
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
SOT23-5: plastic small outline package; 5 leads; body width 1.5 mm
1.35
1.2 1.0
0.025
0.55 0.41
0.22 0.08
3.00 2.70
1.70 1.50
0.55 0.35
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22
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
NOTES
2002 Mar 25
23
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX; SA56616-XX
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 09-02
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 10152
Philips Semiconductors
2002 Mar 25 24

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